DAC of Atmel xmega 128a3u

Notes about the DAC.

1. 12 bit resolution. -  not adjustable.

2. Conversion rates upto 1 million per second capable(as per datasheet)

3. There be 2 ways to trigger conversion on the DAC.

     a) The data registers are written(when high byte register is updated)

     b) Incoming event from xmega event system.(value in register when event arrives is converted)

Different trigger for the two channels is allowed.

>>>>Trigger mode configured in CTRLB register. 

4. Two data channels but ONLY ONE CONVERSION BLOCK.

>>>>channel operation mode config bits in CTRLB register

4a. Single channel operation - Conversion block always connected to channel 0 register and output channel.

       no sample hold circuit in this mode.

 
5. Refresh Rate -???

6. Voltage references
    a) Bandgap Reference = 1.1V
    b)Analog Vltg supply (Vdd)
    c) External reference(Vref+) >> PIN SHARED WITH THE ADC MODULE.

7. Capable of driving resistive loads of 1 kiloOhm

8. Calibration -
     offset(OFFSETCAL register) and gain(GAINCAL) can be calibrated.
     bit 6 determines direction of calibration, other lower bits decide magnitude.
    *automatic calibration can be done using ADC*
      Manual - 1. set data register value = 0x800 and tune offsetcal till DAC gives exactly half the reference voltage.
                     2. tune the gain value such that 0xFFF gives full reference voltage.
     calibration same for both the channels

9. Right adjusted/ left adjusted values - quite simple to configure.


Reference : Atmel Xmega DAC application notes